Reduction of quiescent leakage current (“IDDQ”) in integrated circuits (“IC”), such as an application specific integrated circuit (“ASIC”), is one goal of integrated circuit design because such a reduction lowers the overall power consumption of the IC. However, implementing features in cells of the IC to reduce the IDDQ also degrades the performance of the cells. Because of the performance degradation, these cells, referred to as “low power cells,” are positioned in electrical paths of the IC where the importance of performance is relatively low. Such selective use of low power cells in an IC reduces IDDQ, which lowers the overall power consumption of the IC without sacrificing the overall performance of the IC.
Conventionally, one feature that distinguishes a low power cell from other cells, such as high performance cells, is a larger cell footprint. The footprint is larger because a low power cell has a gate that is longer than the gate of a high performance cell, which requires the contacts of the low power cell to be further apart from each other. Because of the larger footprint, low power cells may not be used in combination with high performance cells in certain ICs. For example, an ASIC, which requires its cells to have a uniform footprint, cannot benefit from the selective use of low power cells.